#pragma once
#include "config.h"
#include "SkrGraphics/dstorage.h" // IWYU pragma: export

#ifdef __cplusplus
CGPU_EXTERN_C_BEGIN
#endif

// enums
typedef enum ECGPUNvAPI_Status
{
    CGPU_NVAPI_OK = 0, //!< Success. Request is completed.
    CGPU_NVAPI_NONE = 1,
    CGPU_NVAPI_ERROR = -1, //!< Generic error
    CGPU_NVAPI_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUNvAPI_Status;

typedef enum ECGPUAGSReturnCode
{
    CGPU_AGS_SUCCESS,                 ///< Successful function call
    CGPU_AGS_FAILURE,                 ///< Failed to complete call for some unspecified reason
    CGPU_AGS_INVALID_ARGS,            ///< Invalid arguments into the function
    CGPU_AGS_OUT_OF_MEMORY,           ///< Out of memory when allocating space internally
    CGPU_AGS_MISSING_D3D_DLL,         ///< Returned when a D3D dll fails to load
    CGPU_AGS_LEGACY_DRIVER,           ///< Returned if a feature is not present in the installed driver
    CGPU_AGS_NO_AMD_DRIVER_INSTALLED, ///< Returned if the AMD GPU driver does not appear to be installed
    CGPU_AGS_EXTENSION_NOT_SUPPORTED, ///< Returned if the driver does not support the requested driver extension
    CGPU_AGS_ADL_FAILURE,             ///< Failure in ADL (the AMD Display Library)
    CGPU_AGS_DX_FAILURE,              ///< Failure from DirectX runtime
    CGPU_AGS_NONE,
    CGPU_AGS_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUAGSReturnCode;

// Format
typedef enum ECGPUFormat
{
    CGPU_FORMAT_UNDEFINED = 0,
    CGPU_FORMAT_R1_UNORM = 1,
    CGPU_FORMAT_R2_UNORM = 2,
    CGPU_FORMAT_R4_UNORM = 3,
    CGPU_FORMAT_R4G4_UNORM = 4,
    CGPU_FORMAT_G4R4_UNORM = 5,
    CGPU_FORMAT_A8_UNORM = 6,
    CGPU_FORMAT_R8_UNORM = 7,
    CGPU_FORMAT_R8_SNORM = 8,
    CGPU_FORMAT_R8_UINT = 9,
    CGPU_FORMAT_R8_SINT = 10,
    CGPU_FORMAT_R8_SRGB = 11,
    CGPU_FORMAT_B2G3R3_UNORM = 12,
    CGPU_FORMAT_R4G4B4A4_UNORM = 13,
    CGPU_FORMAT_R4G4B4X4_UNORM = 14,
    CGPU_FORMAT_B4G4R4A4_UNORM = 15,
    CGPU_FORMAT_B4G4R4X4_UNORM = 16,
    CGPU_FORMAT_A4R4G4B4_UNORM = 17,
    CGPU_FORMAT_X4R4G4B4_UNORM = 18,
    CGPU_FORMAT_A4B4G4R4_UNORM = 19,
    CGPU_FORMAT_X4B4G4R4_UNORM = 20,
    CGPU_FORMAT_R5G6B5_UNORM = 21,
    CGPU_FORMAT_B5G6R5_UNORM = 22,
    CGPU_FORMAT_R5G5B5A1_UNORM = 23,
    CGPU_FORMAT_B5G5R5A1_UNORM = 24,
    CGPU_FORMAT_A1B5G5R5_UNORM = 25,
    CGPU_FORMAT_A1R5G5B5_UNORM = 26,
    CGPU_FORMAT_R5G5B5X1_UNORM = 27,
    CGPU_FORMAT_B5G5R5X1_UNORM = 28,
    CGPU_FORMAT_X1R5G5B5_UNORM = 29,
    CGPU_FORMAT_X1B5G5R5_UNORM = 30,
    CGPU_FORMAT_B2G3R3A8_UNORM = 31,
    CGPU_FORMAT_R8G8_UNORM = 32,
    CGPU_FORMAT_R8G8_SNORM = 33,
    CGPU_FORMAT_G8R8_UNORM = 34,
    CGPU_FORMAT_G8R8_SNORM = 35,
    CGPU_FORMAT_R8G8_UINT = 36,
    CGPU_FORMAT_R8G8_SINT = 37,
    CGPU_FORMAT_R8G8_SRGB = 38,
    CGPU_FORMAT_R16_UNORM = 39,
    CGPU_FORMAT_R16_SNORM = 40,
    CGPU_FORMAT_R16_UINT = 41,
    CGPU_FORMAT_R16_SINT = 42,
    CGPU_FORMAT_R16_SFLOAT = 43,
    CGPU_FORMAT_R16_SBFLOAT = 44,
    CGPU_FORMAT_R8G8B8_UNORM = 45,
    CGPU_FORMAT_R8G8B8_SNORM = 46,
    CGPU_FORMAT_R8G8B8_UINT = 47,
    CGPU_FORMAT_R8G8B8_SINT = 48,
    CGPU_FORMAT_R8G8B8_SRGB = 49,
    CGPU_FORMAT_B8G8R8_UNORM = 50,
    CGPU_FORMAT_B8G8R8_SNORM = 51,
    CGPU_FORMAT_B8G8R8_UINT = 52,
    CGPU_FORMAT_B8G8R8_SINT = 53,
    CGPU_FORMAT_B8G8R8_SRGB = 54,
    CGPU_FORMAT_R8G8B8A8_UNORM = 55,
    CGPU_FORMAT_R8G8B8A8_SNORM = 56,
    CGPU_FORMAT_R8G8B8A8_UINT = 57,
    CGPU_FORMAT_R8G8B8A8_SINT = 58,
    CGPU_FORMAT_R8G8B8A8_SRGB = 59,
    CGPU_FORMAT_B8G8R8A8_UNORM = 60,
    CGPU_FORMAT_B8G8R8A8_SNORM = 61,
    CGPU_FORMAT_B8G8R8A8_UINT = 62,
    CGPU_FORMAT_B8G8R8A8_SINT = 63,
    CGPU_FORMAT_B8G8R8A8_SRGB = 64,
    CGPU_FORMAT_R8G8B8X8_UNORM = 65,
    CGPU_FORMAT_B8G8R8X8_UNORM = 66,
    CGPU_FORMAT_R16G16_UNORM = 67,
    CGPU_FORMAT_G16R16_UNORM = 68,
    CGPU_FORMAT_R16G16_SNORM = 69,
    CGPU_FORMAT_G16R16_SNORM = 70,
    CGPU_FORMAT_R16G16_UINT = 71,
    CGPU_FORMAT_R16G16_SINT = 72,
    CGPU_FORMAT_R16G16_SFLOAT = 73,
    CGPU_FORMAT_R16G16_SBFLOAT = 74,
    CGPU_FORMAT_R32_UINT = 75,
    CGPU_FORMAT_R32_SINT = 76,
    CGPU_FORMAT_R32_SFLOAT = 77,
    CGPU_FORMAT_A2R10G10B10_UNORM = 78,
    CGPU_FORMAT_A2R10G10B10_UINT = 79,
    CGPU_FORMAT_A2R10G10B10_SNORM = 80,
    CGPU_FORMAT_A2R10G10B10_SINT = 81,
    CGPU_FORMAT_A2B10G10R10_UNORM = 82,
    CGPU_FORMAT_A2B10G10R10_UINT = 83,
    CGPU_FORMAT_A2B10G10R10_SNORM = 84,
    CGPU_FORMAT_A2B10G10R10_SINT = 85,
    CGPU_FORMAT_R10G10B10A2_UNORM = 86,
    CGPU_FORMAT_R10G10B10A2_UINT = 87,
    CGPU_FORMAT_R10G10B10A2_SNORM = 88,
    CGPU_FORMAT_R10G10B10A2_SINT = 89,
    CGPU_FORMAT_B10G10R10A2_UNORM = 90,
    CGPU_FORMAT_B10G10R10A2_UINT = 91,
    CGPU_FORMAT_B10G10R10A2_SNORM = 92,
    CGPU_FORMAT_B10G10R10A2_SINT = 93,
    CGPU_FORMAT_B10G11R11_UFLOAT = 94,
    CGPU_FORMAT_E5B9G9R9_UFLOAT = 95,
    CGPU_FORMAT_R16G16B16_UNORM = 96,
    CGPU_FORMAT_R16G16B16_SNORM = 97,
    CGPU_FORMAT_R16G16B16_UINT = 98,
    CGPU_FORMAT_R16G16B16_SINT = 99,
    CGPU_FORMAT_R16G16B16_SFLOAT = 100,
    CGPU_FORMAT_R16G16B16_SBFLOAT = 101,
    CGPU_FORMAT_R16G16B16A16_UNORM = 102,
    CGPU_FORMAT_R16G16B16A16_SNORM = 103,
    CGPU_FORMAT_R16G16B16A16_UINT = 104,
    CGPU_FORMAT_R16G16B16A16_SINT = 105,
    CGPU_FORMAT_R16G16B16A16_SFLOAT = 106,
    CGPU_FORMAT_R16G16B16A16_SBFLOAT = 107,
    CGPU_FORMAT_R32G32_UINT = 108,
    CGPU_FORMAT_R32G32_SINT = 109,
    CGPU_FORMAT_R32G32_SFLOAT = 110,
    CGPU_FORMAT_R32G32B32_UINT = 111,
    CGPU_FORMAT_R32G32B32_SINT = 112,
    CGPU_FORMAT_R32G32B32_SFLOAT = 113,
    CGPU_FORMAT_R32G32B32A32_UINT = 114,
    CGPU_FORMAT_R32G32B32A32_SINT = 115,
    CGPU_FORMAT_R32G32B32A32_SFLOAT = 116,
    CGPU_FORMAT_R64_UINT = 117,
    CGPU_FORMAT_R64_SINT = 118,
    CGPU_FORMAT_R64_SFLOAT = 119,
    CGPU_FORMAT_R64G64_UINT = 120,
    CGPU_FORMAT_R64G64_SINT = 121,
    CGPU_FORMAT_R64G64_SFLOAT = 122,
    CGPU_FORMAT_R64G64B64_UINT = 123,
    CGPU_FORMAT_R64G64B64_SINT = 124,
    CGPU_FORMAT_R64G64B64_SFLOAT = 125,
    CGPU_FORMAT_R64G64B64A64_UINT = 126,
    CGPU_FORMAT_R64G64B64A64_SINT = 127,
    CGPU_FORMAT_R64G64B64A64_SFLOAT = 128,
    CGPU_FORMAT_D16_UNORM = 129,
    CGPU_FORMAT_X8_D24_UNORM = 130,
    CGPU_FORMAT_D32_SFLOAT = 131,
    CGPU_FORMAT_S8_UINT = 132,
    CGPU_FORMAT_D16_UNORM_S8_UINT = 133,
    CGPU_FORMAT_D24_UNORM_S8_UINT = 134,
    CGPU_FORMAT_D32_SFLOAT_S8_UINT = 135,
    CGPU_FORMAT_DXBC1_RGB_UNORM = 136,
    CGPU_FORMAT_DXBC1_RGB_SRGB = 137,
    CGPU_FORMAT_DXBC1_RGBA_UNORM = 138,
    CGPU_FORMAT_DXBC1_RGBA_SRGB = 139,
    CGPU_FORMAT_DXBC2_UNORM = 140,
    CGPU_FORMAT_DXBC2_SRGB = 141,
    CGPU_FORMAT_DXBC3_UNORM = 142,
    CGPU_FORMAT_DXBC3_SRGB = 143,
    CGPU_FORMAT_DXBC4_UNORM = 144,
    CGPU_FORMAT_DXBC4_SNORM = 145,
    CGPU_FORMAT_DXBC5_UNORM = 146,
    CGPU_FORMAT_DXBC5_SNORM = 147,
    CGPU_FORMAT_DXBC6H_UFLOAT = 148,
    CGPU_FORMAT_DXBC6H_SFLOAT = 149,
    CGPU_FORMAT_DXBC7_UNORM = 150,
    CGPU_FORMAT_DXBC7_SRGB = 151,
    CGPU_FORMAT_PVRTC1_2BPP_UNORM = 152,
    CGPU_FORMAT_PVRTC1_4BPP_UNORM = 153,
    CGPU_FORMAT_PVRTC2_2BPP_UNORM = 154,
    CGPU_FORMAT_PVRTC2_4BPP_UNORM = 155,
    CGPU_FORMAT_PVRTC1_2BPP_SRGB = 156,
    CGPU_FORMAT_PVRTC1_4BPP_SRGB = 157,
    CGPU_FORMAT_PVRTC2_2BPP_SRGB = 158,
    CGPU_FORMAT_PVRTC2_4BPP_SRGB = 159,
    CGPU_FORMAT_ETC2_R8G8B8_UNORM = 160,
    CGPU_FORMAT_ETC2_R8G8B8_SRGB = 161,
    CGPU_FORMAT_ETC2_R8G8B8A1_UNORM = 162,
    CGPU_FORMAT_ETC2_R8G8B8A1_SRGB = 163,
    CGPU_FORMAT_ETC2_R8G8B8A8_UNORM = 164,
    CGPU_FORMAT_ETC2_R8G8B8A8_SRGB = 165,
    CGPU_FORMAT_ETC2_EAC_R11_UNORM = 166,
    CGPU_FORMAT_ETC2_EAC_R11_SNORM = 167,
    CGPU_FORMAT_ETC2_EAC_R11G11_UNORM = 168,
    CGPU_FORMAT_ETC2_EAC_R11G11_SNORM = 169,
    CGPU_FORMAT_ASTC_4x4_UNORM = 170,
    CGPU_FORMAT_ASTC_4x4_SRGB = 171,
    CGPU_FORMAT_ASTC_5x4_UNORM = 172,
    CGPU_FORMAT_ASTC_5x4_SRGB = 173,
    CGPU_FORMAT_ASTC_5x5_UNORM = 174,
    CGPU_FORMAT_ASTC_5x5_SRGB = 175,
    CGPU_FORMAT_ASTC_6x5_UNORM = 176,
    CGPU_FORMAT_ASTC_6x5_SRGB = 177,
    CGPU_FORMAT_ASTC_6x6_UNORM = 178,
    CGPU_FORMAT_ASTC_6x6_SRGB = 179,
    CGPU_FORMAT_ASTC_8x5_UNORM = 180,
    CGPU_FORMAT_ASTC_8x5_SRGB = 181,
    CGPU_FORMAT_ASTC_8x6_UNORM = 182,
    CGPU_FORMAT_ASTC_8x6_SRGB = 183,
    CGPU_FORMAT_ASTC_8x8_UNORM = 184,
    CGPU_FORMAT_ASTC_8x8_SRGB = 185,
    CGPU_FORMAT_ASTC_10x5_UNORM = 186,
    CGPU_FORMAT_ASTC_10x5_SRGB = 187,
    CGPU_FORMAT_ASTC_10x6_UNORM = 188,
    CGPU_FORMAT_ASTC_10x6_SRGB = 189,
    CGPU_FORMAT_ASTC_10x8_UNORM = 190,
    CGPU_FORMAT_ASTC_10x8_SRGB = 191,
    CGPU_FORMAT_ASTC_10x10_UNORM = 192,
    CGPU_FORMAT_ASTC_10x10_SRGB = 193,
    CGPU_FORMAT_ASTC_12x10_UNORM = 194,
    CGPU_FORMAT_ASTC_12x10_SRGB = 195,
    CGPU_FORMAT_ASTC_12x12_UNORM = 196,
    CGPU_FORMAT_ASTC_12x12_SRGB = 197,
    CGPU_FORMAT_CLUT_P4 = 198,
    CGPU_FORMAT_CLUT_P4A4 = 199,
    CGPU_FORMAT_CLUT_P8 = 200,
    CGPU_FORMAT_CLUT_P8A8 = 201,
    CGPU_FORMAT_R4G4B4A4_UNORM_PACK16 = 202,
    CGPU_FORMAT_B4G4R4A4_UNORM_PACK16 = 203,
    CGPU_FORMAT_R5G6B5_UNORM_PACK16 = 204,
    CGPU_FORMAT_B5G6R5_UNORM_PACK16 = 205,
    CGPU_FORMAT_R5G5B5A1_UNORM_PACK16 = 206,
    CGPU_FORMAT_B5G5R5A1_UNORM_PACK16 = 207,
    CGPU_FORMAT_A1R5G5B5_UNORM_PACK16 = 208,
    CGPU_FORMAT_G16B16G16R16_422_UNORM = 209,
    CGPU_FORMAT_B16G16R16G16_422_UNORM = 210,
    CGPU_FORMAT_R12X4G12X4B12X4A12X4_UNORM_4PACK16 = 211,
    CGPU_FORMAT_G12X4B12X4G12X4R12X4_422_UNORM_4PACK16 = 212,
    CGPU_FORMAT_B12X4G12X4R12X4G12X4_422_UNORM_4PACK16 = 213,
    CGPU_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16 = 214,
    CGPU_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16 = 215,
    CGPU_FORMAT_B10X6G10X6R10X6G10X6_422_UNORM_4PACK16 = 216,
    CGPU_FORMAT_G8B8G8R8_422_UNORM = 217,
    CGPU_FORMAT_B8G8R8G8_422_UNORM = 218,
    CGPU_FORMAT_G8_B8_R8_3PLANE_420_UNORM = 219,
    CGPU_FORMAT_G8_B8R8_2PLANE_420_UNORM = 220,
    CGPU_FORMAT_G8_B8_R8_3PLANE_422_UNORM = 221,
    CGPU_FORMAT_G8_B8R8_2PLANE_422_UNORM = 222,
    CGPU_FORMAT_G8_B8_R8_3PLANE_444_UNORM = 223,
    CGPU_FORMAT_G10X6_B10X6_R10X6_3PLANE_420_UNORM_3PACK16 = 224,
    CGPU_FORMAT_G10X6_B10X6_R10X6_3PLANE_422_UNORM_3PACK16 = 225,
    CGPU_FORMAT_G10X6_B10X6_R10X6_3PLANE_444_UNORM_3PACK16 = 226,
    CGPU_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16 = 227,
    CGPU_FORMAT_G10X6_B10X6R10X6_2PLANE_422_UNORM_3PACK16 = 228,
    CGPU_FORMAT_G12X4_B12X4_R12X4_3PLANE_420_UNORM_3PACK16 = 229,
    CGPU_FORMAT_G12X4_B12X4_R12X4_3PLANE_422_UNORM_3PACK16 = 230,
    CGPU_FORMAT_G12X4_B12X4_R12X4_3PLANE_444_UNORM_3PACK16 = 231,
    CGPU_FORMAT_G12X4_B12X4R12X4_2PLANE_420_UNORM_3PACK16 = 232,
    CGPU_FORMAT_G12X4_B12X4R12X4_2PLANE_422_UNORM_3PACK16 = 233,
    CGPU_FORMAT_G16_B16_R16_3PLANE_420_UNORM = 234,
    CGPU_FORMAT_G16_B16_R16_3PLANE_422_UNORM = 235,
    CGPU_FORMAT_G16_B16_R16_3PLANE_444_UNORM = 236,
    CGPU_FORMAT_G16_B16R16_2PLANE_420_UNORM = 237,
    CGPU_FORMAT_G16_B16R16_2PLANE_422_UNORM = 238,
    CGPU_FORMAT_COUNT = CGPU_FORMAT_G16_B16R16_2PLANE_422_UNORM + 1,
    CGPU_FORMAT_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUFormat;

typedef enum ECGPUChannelBit
{
    CGPU_CHANNEL_INVALID = 0,
    CGPU_CHANNEL_R = 0x00000001,
    CGPU_CHANNEL_G = 0x00000002,
    CGPU_CHANNEL_B = 0x00000004,
    CGPU_CHANNEL_A = 0x00000008,
    CGPU_CHANNEL_RG = CGPU_CHANNEL_R | CGPU_CHANNEL_G,
    CGPU_CHANNEL_RGB = CGPU_CHANNEL_R | CGPU_CHANNEL_G | CGPU_CHANNEL_B,
    CGPU_CHANNEL_RGBA = CGPU_CHANNEL_R | CGPU_CHANNEL_G | CGPU_CHANNEL_B | CGPU_CHANNEL_A,
    CGPU_CHANNEL_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUChannelBit;

typedef enum ECGPUSlotMaskBit
{
    CGPU_SLOT_0 = 0x1,
    CGPU_SLOT_1 = 0x2,
    CGPU_SLOT_2 = 0x4,
    CGPU_SLOT_3 = 0x8,
    CGPU_SLOT_4 = 0x10,
    CGPU_SLOT_5 = 0x20,
    CGPU_SLOT_6 = 0x40,
    CGPU_SLOT_7 = 0x80
} ECGPUSlotMaskBit;
typedef uint32_t ECGPUSlotMask;

typedef enum ECGPUFilterType
{
    CGPU_FILTER_TYPE_NEAREST = 0,
    CGPU_FILTER_TYPE_LINEAR,
    CGPU_FILTER_TYPE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUFilterType;

typedef enum ECGPUAddressMode
{
    CGPU_ADDRESS_MODE_MIRROR,
    CGPU_ADDRESS_MODE_REPEAT,
    CGPU_ADDRESS_MODE_CLAMP_TO_EDGE,
    CGPU_ADDRESS_MODE_CLAMP_TO_BORDER,
    CGPU_ADDRESS_MODE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUAddressMode;

typedef enum ECGPUMipMapMode
{
    CGPU_MIPMAP_MODE_NEAREST = 0,
    CGPU_MIPMAP_MODE_LINEAR,
    CGPU_MIPMAP_MODE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUMipMapMode;

typedef enum ECGPULoadAction
{
    CGPU_LOAD_ACTION_DONTCARE,
    CGPU_LOAD_ACTION_LOAD,
    CGPU_LOAD_ACTION_CLEAR,
    CGPU_LOAD_ACTION_COUNT,
    CGPU_LOAD_ACTION_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPULoadAction;

typedef enum ECGPUStoreAction
{
    CGPU_STORE_ACTION_STORE,
    CGPU_STORE_ACTION_DISCARD,
    CGPU_STORE_ACTION_COUNT,
    CGPU_STORE_ACTION_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUStoreAction;

typedef enum ECGPUPrimitiveTopology
{
    CGPU_PRIM_TOPO_POINT_LIST = 0,
    CGPU_PRIM_TOPO_LINE_LIST,
    CGPU_PRIM_TOPO_LINE_STRIP,
    CGPU_PRIM_TOPO_TRI_LIST,
    CGPU_PRIM_TOPO_TRI_STRIP,
    CGPU_PRIM_TOPO_PATCH_LIST,
    CGPU_PRIM_TOPO_COUNT,
    CGPU_PRIM_TOPO_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUPrimitiveTopology;

typedef enum ECGPUBlendConstant
{
    CGPU_BLEND_CONST_ZERO = 0,
    CGPU_BLEND_CONST_ONE,
    CGPU_BLEND_CONST_SRC_COLOR,
    CGPU_BLEND_CONST_ONE_MINUS_SRC_COLOR,
    CGPU_BLEND_CONST_DST_COLOR,
    CGPU_BLEND_CONST_ONE_MINUS_DST_COLOR,
    CGPU_BLEND_CONST_SRC_ALPHA,
    CGPU_BLEND_CONST_ONE_MINUS_SRC_ALPHA,
    CGPU_BLEND_CONST_DST_ALPHA,
    CGPU_BLEND_CONST_ONE_MINUS_DST_ALPHA,
    CGPU_BLEND_CONST_SRC_ALPHA_SATURATE,
    CGPU_BLEND_CONST_BLEND_FACTOR,
    CGPU_BLEND_CONST_ONE_MINUS_BLEND_FACTOR,
    CGPU_BLEND_CONST_COUNT,
    CGPU_BLEND_CONST_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUBlendConstant;

typedef enum ECGPUCullMode
{
    CGPU_CULL_MODE_NONE = 0,
    CGPU_CULL_MODE_BACK,
    CGPU_CULL_MODE_FRONT,
    CGPU_CULL_MODE_BOTH,
    CGPU_CULL_MODE_COUNT,
    CGPU_CULL_MODE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUCullMode;

typedef enum ECGPUFrontFace
{
    CGPU_FRONT_FACE_CCW = 0,
    CGPU_FRONT_FACE_CW,
    CGPU_FRONT_FACE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUFrontFace;

typedef enum ECGPUFillMode
{
    CGPU_FILL_MODE_SOLID,
    CGPU_FILL_MODE_WIREFRAME,
    CGPU_FILL_MODE_COUNT,
    CGPU_FILL_MODE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUFillMode;

typedef enum ECGPUVertexInputRate
{
    CGPU_INPUT_RATE_VERTEX = 0,
    CGPU_INPUT_RATE_INSTANCE = 1,
    CGPU_INPUT_RATE_COUNT,
    CGPU_INPUT_RATE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUVertexInputRate;

typedef enum ECGPUCompareMode
{
    CGPU_CMP_NEVER,
    CGPU_CMP_LESS,
    CGPU_CMP_EQUAL,
    CGPU_CMP_LEQUAL,
    CGPU_CMP_GREATER,
    CGPU_CMP_NOTEQUAL,
    CGPU_CMP_GEQUAL,
    CGPU_CMP_ALWAYS,
    CGPU_CMP_COUNT,
    CGPU_CMP_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUCompareMode;

typedef enum ECGPUStencilFaceFlags
{
    CGPU_STENCIL_FACE_FRONT = 0x00000001,
    CGPU_STENCIL_FACE_BACK = 0x00000002,
    CGPU_STENCIL_FACE_FRONT_AND_BACK = 0x00000003,
    CGPU_STENCIL_FACE_FLAG_BITS_MAX_ENUM = 0x7FFFFFFF
} ECGPUStencilFaceFlags;
typedef uint32_t CGPUStencilFaces;

typedef enum ECGPUStencilOp
{
    CGPU_STENCIL_OP_KEEP,
    CGPU_STENCIL_OP_SET_ZERO,
    CGPU_STENCIL_OP_REPLACE,
    CGPU_STENCIL_OP_INVERT,
    CGPU_STENCIL_OP_INCR,
    CGPU_STENCIL_OP_DECR,
    CGPU_STENCIL_OP_INCR_SAT,
    CGPU_STENCIL_OP_DECR_SAT,
    CGPU_STENCIL_OP_COUNT,
    CGPU_STENCIL_OP_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUStencilOp;

typedef enum ECGPUBlendMode
{
    CGPU_BLEND_MODE_ADD,
    CGPU_BLEND_MODE_SUBTRACT,
    CGPU_BLEND_MODE_REVERSE_SUBTRACT,
    CGPU_BLEND_MODE_MIN,
    CGPU_BLEND_MODE_MAX,
    CGPU_BLEND_MODE_COUNT,
    CGPU_BLEND_MODE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUBlendMode;

typedef enum ECGPUTextureDimension
{
    CGPU_TEXTURE_DIMENSION_1D,
    CGPU_TEXTURE_DIMENSION_2D,
    CGPU_TEXTURE_DIMENSION_2DMS,
    CGPU_TEXTURE_DIMENSION_3D,
    CGPU_TEXTURE_DIMENSION_CUBE,
    CGPU_TEXTURE_DIMENSION_1D_ARRAY,
    CGPU_TEXTURE_DIMENSION_2D_ARRAY,
    CGPU_TEXTURE_DIMENSION_2DMS_ARRAY,
    CGPU_TEXTURE_DIMENSION_CUBE_ARRAY,
    CGPU_TEXTURE_DIMENSION_COUNT,
    CGPU_TEXTURE_DIMENSION_UNDEFINED,
    CGPU_TEXTURE_DIMENSION_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUTextureDimension;

typedef enum ECGPUShaderBytecodeType
{
    CGPU_SHADER_BYTECODE_TYPE_SPIRV = 0,
    CGPU_SHADER_BYTECODE_TYPE_DXIL = 1,
    CGPU_SHADER_BYTECODE_TYPE_MTL = 2,
    CGPU_SHADER_BYTECODE_TYPE_COUNT,
    CGPU_SHADER_BYTECODE_TYPE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUShaderBytecodeType;

static const char* CGPUShaderBytecodeTypeNames[] = {
    "spirv", "dxil", "mtl"
};

// Same Value As Vulkan Enumeration Bits.
typedef enum ECGPUShaderStage
{
    CGPU_SHADER_STAGE_NONE = 0,

    CGPU_SHADER_STAGE_VERT = 0X00000001,
    CGPU_SHADER_STAGE_TESC = 0X00000002,
    CGPU_SHADER_STAGE_TESE = 0X00000004,
    CGPU_SHADER_STAGE_GEOM = 0X00000008,
    CGPU_SHADER_STAGE_FRAG = 0X00000010,
    CGPU_SHADER_STAGE_COMPUTE = 0X00000020,
    CGPU_SHADER_STAGE_RAYTRACING = 0X00000040,

    CGPU_SHADER_STAGE_ALL_GRAPHICS = (uint32_t)CGPU_SHADER_STAGE_VERT | (uint32_t)CGPU_SHADER_STAGE_TESC | (uint32_t)CGPU_SHADER_STAGE_TESE | (uint32_t)CGPU_SHADER_STAGE_GEOM | (uint32_t)CGPU_SHADER_STAGE_FRAG,
    CGPU_SHADER_STAGE_HULL = CGPU_SHADER_STAGE_TESC,
    CGPU_SHADER_STAGE_DOMAIN = CGPU_SHADER_STAGE_TESE,
    CGPU_SHADER_STAGE_COUNT = 6,
    CGPU_SHADER_STAGE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUShaderStage;
typedef uint32_t CGPUShaderStages;

typedef enum ECGPUPipelineStage
{
    CGPU_PIPELINE_STAGE_NONE = 0,

    CGPU_PIPELINE_STAGE_INDEX = 0X00000001,
    CGPU_PIPELINE_STAGE_VERT = 0X00000002,
    CGPU_PIPELINE_STAGE_FRAG = 0X00000004,
    CGPU_PIPELINE_STAGE_DEPTH = 0X00000008,
    CGPU_PIPELINE_STAGE_RENDER_TARGET = 0X00000010,
    CGPU_PIPELINE_STAGE_COMPUTE = 0X00000020,
    CGPU_PIPELINE_STAGE_RAYTRACING = 0X00000040,
    CGPU_PIPELINE_STAGE_COPY = 0X00000080,
    CGPU_PIPELINE_STAGE_RESOLVE = 0X00000100,
    CGPU_PIPELINE_STAGE_EXECUTE_INDIRECT = 0X00000200,
    CGPU_PIPELINE_STAGE_PREDICATION = CGPU_PIPELINE_STAGE_EXECUTE_INDIRECT,

    // TODO: Handle AS COPY / BUILD

    CGPU_PIPELINE_STAGE_COUNT = 10,
    CGPU_PIPELINE_STAGE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUPipelineStage;
typedef uint32_t CGPUShaderStages;

typedef enum ECGPUFenceStatus
{
    CGPU_FENCE_STATUS_COMPLETE = 0,
    CGPU_FENCE_STATUS_INCOMPLETE,
    CGPU_FENCE_STATUS_NOTSUBMITTED,
    CGPU_FENCE_STATUS_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUFenceStatus;

typedef enum ECGPUQueryType
{
    CGPU_QUERY_TYPE_TIMESTAMP = 0,
    CGPU_QUERY_TYPE_PIPELINE_STATISTICS,
    CGPU_QUERY_TYPE_OCCLUSION,
    CGPU_QUERY_TYPE_COUNT,
} ECGPUQueryType;

typedef enum ECGPUResourceState
{
    CGPU_RESOURCE_STATE_UNDEFINED = 0,
    CGPU_RESOURCE_STATE_VERTEX_AND_CONSTANT_BUFFER = 0x1,
    CGPU_RESOURCE_STATE_INDEX_BUFFER = 0x2,
    CGPU_RESOURCE_STATE_RENDER_TARGET = 0x4,
    CGPU_RESOURCE_STATE_UNORDERED_ACCESS = 0x8,
    CGPU_RESOURCE_STATE_DEPTH_WRITE = 0x10,
    CGPU_RESOURCE_STATE_DEPTH_READ = 0x20,
    CGPU_RESOURCE_STATE_NON_PIXEL_SHADER_RESOURCE = 0x40,
    CGPU_RESOURCE_STATE_PIXEL_SHADER_RESOURCE = 0x40 | 0x80,
    CGPU_RESOURCE_STATE_SHADER_RESOURCE = 0x40 | 0x80,
    CGPU_RESOURCE_STATE_STREAM_OUT = 0x100,
    CGPU_RESOURCE_STATE_INDIRECT_ARGUMENT = 0x200,
    CGPU_RESOURCE_STATE_COPY_DEST = 0x400,
    CGPU_RESOURCE_STATE_COPY_SOURCE = 0x800,
    CGPU_RESOURCE_STATE_GENERIC_READ = (((((0x1 | 0x2) | 0x40) | 0x80) | 0x200) | 0x800),
    CGPU_RESOURCE_STATE_PRESENT = 0x1000,
    CGPU_RESOURCE_STATE_COMMON = 0x2000,
    CGPU_RESOURCE_STATE_ACCELERATION_STRUCTURE_READ = 0x4000,
    CGPU_RESOURCE_STATE_ACCELERATION_STRUCTURE_WRITE = 0x8000,
    CGPU_RESOURCE_STATE_SHADING_RATE_SOURCE = 0x10000,
    CGPU_RESOURCE_STATE_RESOLVE_DEST = 0x20000,
    CGPU_RESOURCE_STATE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUResourceState;
typedef uint32_t CGPUResourceStates;

typedef enum ECGPUMemoryUsage
{
    /// No intended memory usage specified.
    CGPU_MEM_USAGE_UNKNOWN = 0,
    /// Memory will be used on device only, no need to be mapped on host.
    CGPU_MEM_USAGE_GPU_ONLY = 1,
    /// Memory will be mapped on host. Could be used for transfer to device.
    CGPU_MEM_USAGE_CPU_ONLY = 2,
    /// Memory will be used for frequent (dynamic) updates from host and reads on device.
    /// Memory location (heap) is unsure.
    CGPU_MEM_USAGE_CPU_TO_GPU = 3,
    /// Memory will be used for writing on device and readback on host.
    /// Memory location (heap) is unsure.
    CGPU_MEM_USAGE_GPU_TO_CPU = 4,
    CGPU_MEM_USAGE_COUNT,
    CGPU_MEM_USAGE_MAX_ENUM = 0x7FFFFFFF
} ECGPUMemoryUsage;
typedef uint32_t CGPUMemoryUsages;

typedef enum ECGPUMemoryPoolType
{
    CGPU_MEM_POOL_TYPE_AUTOMATIC = 0,
    CGPU_MEM_POOL_TYPE_LINEAR = 1,
    CGPU_MEM_POOL_TYPE_TILED = 2,
    CGPU_MEM_POOL_TYPE_COUNT,
    CGPU_MEM_POOL_TYPE_MAX_ENUM = 0x7FFFFFFF
} ECGPUMemoryPoolType;

typedef enum ECGPUMemoryPoolFlag
{
    CGPU_MEM_POOL_FLAG_NONE = 0,
    CGPU_MEM_POOL_FLAG_ALLOW_BUFFERS = 0x01,     // 允许 Buffer
    CGPU_MEM_POOL_FLAG_ALLOW_TEXTURES = 0x02,    // 允许 Texture（非 RT/DS）
    CGPU_MEM_POOL_FLAG_ALLOW_RW = 0x04,          // 允许 RW（UAV）资源
    CGPU_MEM_POOL_FLAG_ALLOW_RT_DS = 0x08,       // 允许 RenderTarget/DepthStencil
    CGPU_MEM_POOL_FLAG_MAX_ENUM = 0x7FFFFFFF
} ECGPUMemoryPoolFlag;
typedef uint32_t CGPUMemoryPoolFlags;

typedef enum ECGPUBufferFlag
{
    /// Default flag (Buffer will use aliased memory, buffer will not be cpu accessible until mapBuffer is called)
    CGPU_BUFFER_FLAG_NONE = 0,
    /// Buffer will allocate its own memory (COMMITTED resource)
    CGPU_BUFFER_FLAG_DEDICATED_BIT = 0x02,
    /// Buffer will be persistently mapped
    CGPU_BUFFER_FLAG_PERSISTENT_MAP_BIT = 0x04,
    /// Use ESRAM to store this buffer
    CGPU_BUFFER_FLAG_ESRAM = 0x08,
    /// Flag to specify to create GPUOnly buffer as Host visible
    CGPU_BUFFER_FLAG_HOST_VISIBLE = 0x20,
    CGPU_BUFFER_FLAG_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUBufferFlag;
typedef uint32_t CGPUBufferFlags;

typedef enum ECGPUTextureFlag
{
    /// Default flag (Texture will use default allocation strategy decided by the api specific allocator)
    CGPU_TEXTURE_FLAG_NONE = 0,
    /// Texture will allocate its own memory (COMMITTED resource)
    /// Note that this flag is not restricted Commited/Dedicated Allocation
    /// Actually VMA/D3D12MA allocate dedicated memories with ALLOW_ALIAS flag with specific loacl heaps
    /// If the texture needs to be restricted Committed/Dedicated(thus you want to keep its priority high)
    /// Toggle is_restrict_dedicated flag in CGPUTextureDescriptor
    CGPU_TEXTURE_FLAG_DEDICATED_BIT = 0x01,
    /// Texture will be allocated in memory which can be shared among multiple processes
    CGPU_TEXTURE_FLAG_EXPORT_BIT = 0x02,
    /// Texture will be allocated in memory which can be shared among multiple gpus
    CGPU_TEXTURE_FLAG_EXPORT_ADAPTER_BIT = 0x04,
    /// Use on-tile memory to store this texture
    CGPU_TEXTURE_FLAG_ON_TILE = 0x08,
    /// Prevent compression meta data from generating (XBox)
    CGPU_TEXTURE_FLAG_NO_COMPRESSION = 0x10,
    /// Force 2D instead of automatically determining dimension based on width, height, depth
    CGPU_TEXTURE_FLAG_FORCE_2D = 0x20,
    /// Force 3D instead of automatically determining dimension based on width, height, depth
    CGPU_TEXTURE_FLAG_FORCE_3D = 0x40,
    /// Display target
    CGPU_TEXTURE_FLAG_ALLOW_DISPLAY_TARGET = 0x80,
    /// Create a normal map texture
    CGPU_TEXTURE_FLAG_NORMAL_MAP = 0x100,
    /// Fragment mask
    CGPU_TEXTURE_FLAG_FRAG_MASK = 0x200,
    /// Create as AliasingResource
    CGPU_TEXTURE_FLAG_ALIASING_RESOURCE = 0x400,
    /// Create as TiledResource
    CGPU_TEXTURE_FLAG_TILED_RESOURCE = 0x800,
    /// 
    CGPU_TEXTURE_FLAG_USABLE_MAX = 0x40000,
    CGPU_TEXTURE_FLAG_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUTextureFlag;
typedef uint32_t CGPUTextureFlags;

typedef enum ECGPUSampleCount
{
    CGPU_SAMPLE_COUNT_1 = 1,
    CGPU_SAMPLE_COUNT_2 = 2,
    CGPU_SAMPLE_COUNT_4 = 4,
    CGPU_SAMPLE_COUNT_8 = 8,
    CGPU_SAMPLE_COUNT_16 = 16,
    CGPU_SAMPLE_COUNT_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUSampleCount;

typedef enum ECGPUPipelineType
{
    CGPU_PIPELINE_TYPE_NONE = 0,
    CGPU_PIPELINE_TYPE_COMPUTE,
    CGPU_PIPELINE_TYPE_GRAPHICS,
    CGPU_PIPELINE_TYPE_RAYTRACING,
    CGPU_PIPELINE_TYPE_COUNT,
    CGPU_PIPELINE_TYPE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUPipelineType;

typedef enum ECGPUResourceType
{
    CGPU_RESOURCE_TYPE2_NONE = 0,
    CGPU_RESOURCE_TYPE2_SAMPLER = 0x00000001,
    CGPU_RESOURCE_TYPE2_BUFFER = (CGPU_RESOURCE_TYPE2_SAMPLER << 1),
    CGPU_RESOURCE_TYPE2_TEXTURE = (CGPU_RESOURCE_TYPE2_BUFFER << 1),
    CGPU_RESOURCE_TYPE2_ACCELERATION_STRUCTURE = (CGPU_RESOURCE_TYPE2_TEXTURE << 1),
    CGPU_RESOURCE_TYPE2_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUResourceType;

typedef enum ECGPUBufferUsage
{
    CGPU_BUFFER_USAGE_NONE = 0,
    CGPU_BUFFER_USAGE_SHADER_READ = 1,
    CGPU_BUFFER_USAGE_SHADER_READWRITE = (CGPU_BUFFER_USAGE_SHADER_READ << 1),

    CGPU_BUFFER_USAGE_CONSTANT_BUFFER = (CGPU_BUFFER_USAGE_SHADER_READWRITE << 1),
    CGPU_BUFFER_USAGE_INDEX_BUFFER = (CGPU_BUFFER_USAGE_SHADER_READWRITE << 1),
    CGPU_BUFFER_USAGE_VERTEX_BUFFER = (CGPU_BUFFER_USAGE_INDEX_BUFFER << 1),
    CGPU_BUFFER_USAGE_ACCELERATION_STRUCTURE = (CGPU_BUFFER_USAGE_VERTEX_BUFFER << 1),

    CGPU_BUFFER_USAGE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUBufferUsage;
typedef uint32_t CGPUBufferUsages;

typedef enum ECGPUTextureUsage
{
    CGPU_TEXTURE_USAGE_NONE = 0,
    CGPU_TEXTURE_USAGE_SHADER_READ = 1,
    CGPU_TEXTURE_USAGE_SHADER_READWRITE = (CGPU_TEXTURE_USAGE_SHADER_READ << 1),

    CGPU_TEXTURE_USAGE_RENDER_TARGET = (CGPU_TEXTURE_USAGE_SHADER_READWRITE << 1),
    CGPU_TEXTURE_USAGE_DEPTH_STENCIL = (CGPU_TEXTURE_USAGE_RENDER_TARGET << 1),
    CGPU_TEXTURE_USAGE_CUBEMAP = (CGPU_TEXTURE_USAGE_DEPTH_STENCIL << 1),

    CGPU_TEXTURE_USAGE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUTextureUsage;
typedef uint32_t CGPUTextureUsages;

typedef enum ECGPUViewUsage
{
    CGPU_BUFFER_VIEW_USAGE_CBV = 0x01,

    CGPU_BUFFER_VIEW_USAGE_UAV_STRUCTURED = 0x10,
    CGPU_BUFFER_VIEW_USAGE_UAV_RAW = 0x20,
    CGPU_BUFFER_VIEW_USAGE_UAV_TEXEL = 0x40,

    CGPU_BUFFER_VIEW_USAGE_SRV_STRUCTURED = 0x100,
    CGPU_BUFFER_VIEW_USAGE_SRV_RAW = 0x200,
    CGPU_BUFFER_VIEW_USAGE_SRV_TEXEL = 0x400,
    CGPU_BUFFER_VIEW_USAGE_PUSH_CONSTANT = 0x800,

    CGPU_TEXTURE_VIEW_USAGE_SRV = 0x1000,
    CGPU_TEXTURE_VIEW_USAGE_RTV_DSV = 0x2000,
    CGPU_TEXTURE_VIEW_USAGE_UAV = 0x4000,

    CGPU_BUFFER_VIEW_USAGE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUViewUsage;
typedef uint32_t CGPUViewUsages;
typedef uint32_t CGPUBufferViewUsages;
typedef uint32_t CGPUTextureViewUsages;

typedef enum ECGPUTextureViewAspect
{
    CGPU_TEXTURE_VIEW_ASPECTS_COLOR = 0x01,
    CGPU_TEXTURE_VIEW_ASPECTS_DEPTH = 0x02,
    CGPU_TEXTURE_VIEW_ASPECTS_STENCIL = 0x04,
    CGPU_TEXTURE_VIEW_ASPECTS_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUTextureViewAspect;
typedef uint32_t CGPUTextureViewAspects;

// VRS
typedef enum ECGPUShadingRate
{
	CGPU_SHADING_RATE_FULL = 0,
	CGPU_SHADING_RATE_HALF = CGPU_SHADING_RATE_FULL + 1,
	CGPU_SHADING_RATE_QUARTER = CGPU_SHADING_RATE_HALF + 1,
	CGPU_SHADING_RATE_1X2 = CGPU_SHADING_RATE_QUARTER + 1,
	CGPU_SHADING_RATE_2X1 = CGPU_SHADING_RATE_1X2 + 1,
    // Causes low wave usage, avoid using this! Just using 2x2.
	CGPU_SHADING_RATE_2X4 = CGPU_SHADING_RATE_2X1 + 1,
    // Causes low wave usage, avoid using this! Just using 2x2.
    CGPU_SHADING_RATE_4X2 = CGPU_SHADING_RATE_2X4 + 1,
	CGPU_SHADING_RATE_COUNT = CGPU_SHADING_RATE_4X2 + 1,
    CGPU_SHADING_RATE_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUShadingRate;

typedef enum ECGPUShadingRateCombiner
{
	CGPU_SHADING_RATE_COMBINER_PASSTHROUGH = 0,
	CGPU_SHADING_RATE_COMBINER_OVERRIDE = 1,
	CGPU_SHADING_RATE_COMBINER_MIN = 2,
	CGPU_SHADING_RATE_COMBINER_MAX = 3,
	CGPU_SHADING_RATE_COMBINER_SUM = 4,
	CGPU_SHADING_RATE_COMBINER_MAX_ENUM_BIT = 0x7FFFFFFF
} ECGPUShadingRateCombiner;

// DStorage
typedef enum ESkrDStorageAvailability ECGPUDStorageAvailability;
typedef enum ESkrDStorageSource ECGPUDStorageSource;
typedef enum ESkrDStoragePriority ECGPUDStoragePriority;
typedef enum ESkrDStorageCompression ECGPUDStorageCompression;
typedef SkrDStorageCompression CGPUDStorageCompression;

/* clang-format off */
static SKR_FORCEINLINE bool FormatUtil_IsDepthStencilFormat(ECGPUFormat const fmt) {
    switch(fmt) {
        case CGPU_FORMAT_D24_UNORM_S8_UINT:
        case CGPU_FORMAT_D32_SFLOAT_S8_UINT:
        case CGPU_FORMAT_D32_SFLOAT:
        case CGPU_FORMAT_X8_D24_UNORM:
        case CGPU_FORMAT_D16_UNORM:
        case CGPU_FORMAT_D16_UNORM_S8_UINT:
            return true;
        default: return false;
    }
    return false;
}

static SKR_FORCEINLINE bool FormatUtil_IsDepthOnlyFormat(ECGPUFormat const fmt) {
    switch(fmt) {
        case CGPU_FORMAT_D32_SFLOAT:
        case CGPU_FORMAT_D16_UNORM:
            return true;
        default: return false;
    }
    return false;
}

static SKR_FORCEINLINE uint32_t FormatUtil_BitSizeOfBlock(ECGPUFormat const fmt) {
	switch(fmt) {
		case CGPU_FORMAT_UNDEFINED: return 0;
		case CGPU_FORMAT_R1_UNORM: return 8;
		case CGPU_FORMAT_R2_UNORM: return 8;
		case CGPU_FORMAT_R4_UNORM: return 8;
		case CGPU_FORMAT_R4G4_UNORM: return 8;
		case CGPU_FORMAT_G4R4_UNORM: return 8;
		case CGPU_FORMAT_A8_UNORM: return 8;
		case CGPU_FORMAT_R8_UNORM: return 8;
		case CGPU_FORMAT_R8_SNORM: return 8;
		case CGPU_FORMAT_R8_UINT: return 8;
		case CGPU_FORMAT_R8_SINT: return 8;
		case CGPU_FORMAT_R8_SRGB: return 8;
		case CGPU_FORMAT_B2G3R3_UNORM: return 8;
		case CGPU_FORMAT_R4G4B4A4_UNORM: return 16;
		case CGPU_FORMAT_R4G4B4X4_UNORM: return 16;
		case CGPU_FORMAT_B4G4R4A4_UNORM: return 16;
		case CGPU_FORMAT_B4G4R4X4_UNORM: return 16;
		case CGPU_FORMAT_A4R4G4B4_UNORM: return 16;
		case CGPU_FORMAT_X4R4G4B4_UNORM: return 16;
		case CGPU_FORMAT_A4B4G4R4_UNORM: return 16;
		case CGPU_FORMAT_X4B4G4R4_UNORM: return 16;
		case CGPU_FORMAT_R5G6B5_UNORM: return 16;
		case CGPU_FORMAT_B5G6R5_UNORM: return 16;
		case CGPU_FORMAT_R5G5B5A1_UNORM: return 16;
		case CGPU_FORMAT_B5G5R5A1_UNORM: return 16;
		case CGPU_FORMAT_A1B5G5R5_UNORM: return 16;
		case CGPU_FORMAT_A1R5G5B5_UNORM: return 16;
		case CGPU_FORMAT_R5G5B5X1_UNORM: return 16;
		case CGPU_FORMAT_B5G5R5X1_UNORM: return 16;
		case CGPU_FORMAT_X1R5G5B5_UNORM: return 16;
		case CGPU_FORMAT_X1B5G5R5_UNORM: return 16;
		case CGPU_FORMAT_B2G3R3A8_UNORM: return 16;
		case CGPU_FORMAT_R8G8_UNORM: return 16;
		case CGPU_FORMAT_R8G8_SNORM: return 16;
		case CGPU_FORMAT_G8R8_UNORM: return 16;
		case CGPU_FORMAT_G8R8_SNORM: return 16;
		case CGPU_FORMAT_R8G8_UINT: return 16;
		case CGPU_FORMAT_R8G8_SINT: return 16;
		case CGPU_FORMAT_R8G8_SRGB: return 16;
		case CGPU_FORMAT_R16_UNORM: return 16;
		case CGPU_FORMAT_R16_SNORM: return 16;
		case CGPU_FORMAT_R16_UINT: return 16;
		case CGPU_FORMAT_R16_SINT: return 16;
		case CGPU_FORMAT_R16_SFLOAT: return 16;
		case CGPU_FORMAT_R16_SBFLOAT: return 16;
		case CGPU_FORMAT_R8G8B8_UNORM: return 24;
		case CGPU_FORMAT_R8G8B8_SNORM: return 24;
		case CGPU_FORMAT_R8G8B8_UINT: return 24;
		case CGPU_FORMAT_R8G8B8_SINT: return 24;
		case CGPU_FORMAT_R8G8B8_SRGB: return 24;
		case CGPU_FORMAT_B8G8R8_UNORM: return 24;
		case CGPU_FORMAT_B8G8R8_SNORM: return 24;
		case CGPU_FORMAT_B8G8R8_UINT: return 24;
		case CGPU_FORMAT_B8G8R8_SINT: return 24;
		case CGPU_FORMAT_B8G8R8_SRGB: return 24;
		case CGPU_FORMAT_R16G16B16_UNORM: return 48;
		case CGPU_FORMAT_R16G16B16_SNORM: return 48;
		case CGPU_FORMAT_R16G16B16_UINT: return 48;
		case CGPU_FORMAT_R16G16B16_SINT: return 48;
		case CGPU_FORMAT_R16G16B16_SFLOAT: return 48;
		case CGPU_FORMAT_R16G16B16_SBFLOAT: return 48;
		case CGPU_FORMAT_R16G16B16A16_UNORM: return 64;
		case CGPU_FORMAT_R16G16B16A16_SNORM: return 64;
		case CGPU_FORMAT_R16G16B16A16_UINT: return 64;
		case CGPU_FORMAT_R16G16B16A16_SINT: return 64;
		case CGPU_FORMAT_R16G16B16A16_SFLOAT: return 64;
		case CGPU_FORMAT_R16G16B16A16_SBFLOAT: return 64;
		case CGPU_FORMAT_R32G32_UINT: return 64;
		case CGPU_FORMAT_R32G32_SINT: return 64;
		case CGPU_FORMAT_R32G32_SFLOAT: return 64;
		case CGPU_FORMAT_R32G32B32_UINT: return 96;
		case CGPU_FORMAT_R32G32B32_SINT: return 96;
		case CGPU_FORMAT_R32G32B32_SFLOAT: return 96;
		case CGPU_FORMAT_R32G32B32A32_UINT: return 128;
		case CGPU_FORMAT_R32G32B32A32_SINT: return 128;
		case CGPU_FORMAT_R32G32B32A32_SFLOAT: return 128;
		case CGPU_FORMAT_R64_UINT: return 64;
		case CGPU_FORMAT_R64_SINT: return 64;
		case CGPU_FORMAT_R64_SFLOAT: return 64;
		case CGPU_FORMAT_R64G64_UINT: return 128;
		case CGPU_FORMAT_R64G64_SINT: return 128;
		case CGPU_FORMAT_R64G64_SFLOAT: return 128;
		case CGPU_FORMAT_R64G64B64_UINT: return 192;
		case CGPU_FORMAT_R64G64B64_SINT: return 192;
		case CGPU_FORMAT_R64G64B64_SFLOAT: return 192;
		case CGPU_FORMAT_R64G64B64A64_UINT: return 256;
		case CGPU_FORMAT_R64G64B64A64_SINT: return 256;
		case CGPU_FORMAT_R64G64B64A64_SFLOAT: return 256;
		case CGPU_FORMAT_D16_UNORM: return 16;
		case CGPU_FORMAT_S8_UINT: return 8;
		case CGPU_FORMAT_D32_SFLOAT_S8_UINT: return 64;
		case CGPU_FORMAT_DXBC1_RGB_UNORM: return 64;
		case CGPU_FORMAT_DXBC1_RGB_SRGB: return 64;
		case CGPU_FORMAT_DXBC1_RGBA_UNORM: return 64;
		case CGPU_FORMAT_DXBC1_RGBA_SRGB: return 64;
		case CGPU_FORMAT_DXBC2_UNORM: return 128;
		case CGPU_FORMAT_DXBC2_SRGB: return 128;
		case CGPU_FORMAT_DXBC3_UNORM: return 128;
		case CGPU_FORMAT_DXBC3_SRGB: return 128;
		case CGPU_FORMAT_DXBC4_UNORM: return 64;
		case CGPU_FORMAT_DXBC4_SNORM: return 64;
		case CGPU_FORMAT_DXBC5_UNORM: return 128;
		case CGPU_FORMAT_DXBC5_SNORM: return 128;
		case CGPU_FORMAT_DXBC6H_UFLOAT: return 128;
		case CGPU_FORMAT_DXBC6H_SFLOAT: return 128;
		case CGPU_FORMAT_DXBC7_UNORM: return 128;
		case CGPU_FORMAT_DXBC7_SRGB: return 128;
		case CGPU_FORMAT_PVRTC1_2BPP_UNORM: return 64;
		case CGPU_FORMAT_PVRTC1_4BPP_UNORM: return 64;
		case CGPU_FORMAT_PVRTC2_2BPP_UNORM: return 64;
		case CGPU_FORMAT_PVRTC2_4BPP_UNORM: return 64;
		case CGPU_FORMAT_PVRTC1_2BPP_SRGB: return 64;
		case CGPU_FORMAT_PVRTC1_4BPP_SRGB: return 64;
		case CGPU_FORMAT_PVRTC2_2BPP_SRGB: return 64;
		case CGPU_FORMAT_PVRTC2_4BPP_SRGB: return 64;
		case CGPU_FORMAT_ETC2_R8G8B8_UNORM: return 64;
		case CGPU_FORMAT_ETC2_R8G8B8_SRGB: return 64;
		case CGPU_FORMAT_ETC2_R8G8B8A1_UNORM: return 64;
		case CGPU_FORMAT_ETC2_R8G8B8A1_SRGB: return 64;
		case CGPU_FORMAT_ETC2_R8G8B8A8_UNORM: return 64;
		case CGPU_FORMAT_ETC2_R8G8B8A8_SRGB: return 64;
		case CGPU_FORMAT_ETC2_EAC_R11_UNORM: return 64;
		case CGPU_FORMAT_ETC2_EAC_R11_SNORM: return 64;
		case CGPU_FORMAT_ETC2_EAC_R11G11_UNORM: return 64;
		case CGPU_FORMAT_ETC2_EAC_R11G11_SNORM: return 64;
		case CGPU_FORMAT_ASTC_4x4_UNORM: return 128;
		case CGPU_FORMAT_ASTC_4x4_SRGB: return 128;
		case CGPU_FORMAT_ASTC_5x4_UNORM: return 128;
		case CGPU_FORMAT_ASTC_5x4_SRGB: return 128;
		case CGPU_FORMAT_ASTC_5x5_UNORM: return 128;
		case CGPU_FORMAT_ASTC_5x5_SRGB: return 128;
		case CGPU_FORMAT_ASTC_6x5_UNORM: return 128;
		case CGPU_FORMAT_ASTC_6x5_SRGB: return 128;
		case CGPU_FORMAT_ASTC_6x6_UNORM: return 128;
		case CGPU_FORMAT_ASTC_6x6_SRGB: return 128;
		case CGPU_FORMAT_ASTC_8x5_UNORM: return 128;
		case CGPU_FORMAT_ASTC_8x5_SRGB: return 128;
		case CGPU_FORMAT_ASTC_8x6_UNORM: return 128;
		case CGPU_FORMAT_ASTC_8x6_SRGB: return 128;
		case CGPU_FORMAT_ASTC_8x8_UNORM: return 128;
		case CGPU_FORMAT_ASTC_8x8_SRGB: return 128;
		case CGPU_FORMAT_ASTC_10x5_UNORM: return 128;
		case CGPU_FORMAT_ASTC_10x5_SRGB: return 128;
		case CGPU_FORMAT_ASTC_10x6_UNORM: return 128;
		case CGPU_FORMAT_ASTC_10x6_SRGB: return 128;
		case CGPU_FORMAT_ASTC_10x8_UNORM: return 128;
		case CGPU_FORMAT_ASTC_10x8_SRGB: return 128;
		case CGPU_FORMAT_ASTC_10x10_UNORM: return 128;
		case CGPU_FORMAT_ASTC_10x10_SRGB: return 128;
		case CGPU_FORMAT_ASTC_12x10_UNORM: return 128;
		case CGPU_FORMAT_ASTC_12x10_SRGB: return 128;
		case CGPU_FORMAT_ASTC_12x12_UNORM: return 128;
		case CGPU_FORMAT_ASTC_12x12_SRGB: return 128;
		case CGPU_FORMAT_CLUT_P4: return 8;
		case CGPU_FORMAT_CLUT_P4A4: return 8;
		case CGPU_FORMAT_CLUT_P8: return 8;
		case CGPU_FORMAT_CLUT_P8A8: return 16;
		case CGPU_FORMAT_G16B16G16R16_422_UNORM: return 8;
		case CGPU_FORMAT_B16G16R16G16_422_UNORM: return 8;
		case CGPU_FORMAT_R12X4G12X4B12X4A12X4_UNORM_4PACK16: return 8;
		case CGPU_FORMAT_G12X4B12X4G12X4R12X4_422_UNORM_4PACK16: return 8;
		case CGPU_FORMAT_B12X4G12X4R12X4G12X4_422_UNORM_4PACK16: return 8;
		case CGPU_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16: return 8;
		case CGPU_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16: return 8;
		case CGPU_FORMAT_B10X6G10X6R10X6G10X6_422_UNORM_4PACK16: return 8;
		case CGPU_FORMAT_G8B8G8R8_422_UNORM: return 4;
		case CGPU_FORMAT_B8G8R8G8_422_UNORM: return 4;
		default: return 32;
	}
}

static SKR_FORCEINLINE uint32_t FormatUtil_WidthOfBlock(ECGPUFormat const fmt) {
    switch(fmt) {
    case CGPU_FORMAT_UNDEFINED: return 1;
    case CGPU_FORMAT_R1_UNORM: return 8;
    case CGPU_FORMAT_R2_UNORM: return 4;
    case CGPU_FORMAT_R4_UNORM: return 2;
    case CGPU_FORMAT_DXBC1_RGB_UNORM: return 4;
    case CGPU_FORMAT_DXBC1_RGB_SRGB: return 4;
    case CGPU_FORMAT_DXBC1_RGBA_UNORM: return 4;
    case CGPU_FORMAT_DXBC1_RGBA_SRGB: return 4;
    case CGPU_FORMAT_DXBC2_UNORM: return 4;
    case CGPU_FORMAT_DXBC2_SRGB: return 4;
    case CGPU_FORMAT_DXBC3_UNORM: return 4;
    case CGPU_FORMAT_DXBC3_SRGB: return 4;
    case CGPU_FORMAT_DXBC4_UNORM: return 4;
    case CGPU_FORMAT_DXBC4_SNORM: return 4;
    case CGPU_FORMAT_DXBC5_UNORM: return 4;
    case CGPU_FORMAT_DXBC5_SNORM: return 4;
    case CGPU_FORMAT_DXBC6H_UFLOAT: return 4;
    case CGPU_FORMAT_DXBC6H_SFLOAT: return 4;
    case CGPU_FORMAT_DXBC7_UNORM: return 4;
    case CGPU_FORMAT_DXBC7_SRGB: return 4;
    case CGPU_FORMAT_PVRTC1_2BPP_UNORM: return 8;
    case CGPU_FORMAT_PVRTC1_4BPP_UNORM: return 4;
    case CGPU_FORMAT_PVRTC2_2BPP_UNORM: return 8;
    case CGPU_FORMAT_PVRTC2_4BPP_UNORM: return 4;
    case CGPU_FORMAT_PVRTC1_2BPP_SRGB: return 8;
    case CGPU_FORMAT_PVRTC1_4BPP_SRGB: return 4;
    case CGPU_FORMAT_PVRTC2_2BPP_SRGB: return 8;
    case CGPU_FORMAT_PVRTC2_4BPP_SRGB: return 4;
    case CGPU_FORMAT_ETC2_R8G8B8_UNORM: return 4;
    case CGPU_FORMAT_ETC2_R8G8B8_SRGB: return 4;
    case CGPU_FORMAT_ETC2_R8G8B8A1_UNORM: return 4;
    case CGPU_FORMAT_ETC2_R8G8B8A1_SRGB: return 4;
    case CGPU_FORMAT_ETC2_R8G8B8A8_UNORM: return 4;
    case CGPU_FORMAT_ETC2_R8G8B8A8_SRGB: return 4;
    case CGPU_FORMAT_ETC2_EAC_R11_UNORM: return 4;
    case CGPU_FORMAT_ETC2_EAC_R11_SNORM: return 4;
    case CGPU_FORMAT_ETC2_EAC_R11G11_UNORM: return 4;
    case CGPU_FORMAT_ETC2_EAC_R11G11_SNORM: return 4;
    case CGPU_FORMAT_ASTC_4x4_UNORM: return 4;
    case CGPU_FORMAT_ASTC_4x4_SRGB: return 4;
    case CGPU_FORMAT_ASTC_5x4_UNORM: return 5;
    case CGPU_FORMAT_ASTC_5x4_SRGB: return 5;
    case CGPU_FORMAT_ASTC_5x5_UNORM: return 5;
    case CGPU_FORMAT_ASTC_5x5_SRGB: return 5;
    case CGPU_FORMAT_ASTC_6x5_UNORM: return 6;
    case CGPU_FORMAT_ASTC_6x5_SRGB: return 6;
    case CGPU_FORMAT_ASTC_6x6_UNORM: return 6;
    case CGPU_FORMAT_ASTC_6x6_SRGB: return 6;
    case CGPU_FORMAT_ASTC_8x5_UNORM: return 8;
    case CGPU_FORMAT_ASTC_8x5_SRGB: return 8;
    case CGPU_FORMAT_ASTC_8x6_UNORM: return 8;
    case CGPU_FORMAT_ASTC_8x6_SRGB: return 8;
    case CGPU_FORMAT_ASTC_8x8_UNORM: return 8;
    case CGPU_FORMAT_ASTC_8x8_SRGB: return 8;
    case CGPU_FORMAT_ASTC_10x5_UNORM: return 10;
    case CGPU_FORMAT_ASTC_10x5_SRGB: return 10;
    case CGPU_FORMAT_ASTC_10x6_UNORM: return 10;
    case CGPU_FORMAT_ASTC_10x6_SRGB: return 10;
    case CGPU_FORMAT_ASTC_10x8_UNORM: return 10;
    case CGPU_FORMAT_ASTC_10x8_SRGB: return 10;
    case CGPU_FORMAT_ASTC_10x10_UNORM: return 10;
    case CGPU_FORMAT_ASTC_10x10_SRGB: return 10;
    case CGPU_FORMAT_ASTC_12x10_UNORM: return 12;
    case CGPU_FORMAT_ASTC_12x10_SRGB: return 12;
    case CGPU_FORMAT_ASTC_12x12_UNORM: return 12;
    case CGPU_FORMAT_ASTC_12x12_SRGB: return 12;
    case CGPU_FORMAT_CLUT_P4: return 2;
    default: return 1;
	}
}

static SKR_FORCEINLINE uint32_t FormatUtil_HeightOfBlock(ECGPUFormat const fmt) {
	switch(fmt) {
		case CGPU_FORMAT_UNDEFINED: return 1;
		case CGPU_FORMAT_DXBC1_RGB_UNORM: return 4;
		case CGPU_FORMAT_DXBC1_RGB_SRGB: return 4;
		case CGPU_FORMAT_DXBC1_RGBA_UNORM: return 4;
		case CGPU_FORMAT_DXBC1_RGBA_SRGB: return 4;
		case CGPU_FORMAT_DXBC2_UNORM: return 4;
		case CGPU_FORMAT_DXBC2_SRGB: return 4;
		case CGPU_FORMAT_DXBC3_UNORM: return 4;
		case CGPU_FORMAT_DXBC3_SRGB: return 4;
		case CGPU_FORMAT_DXBC4_UNORM: return 4;
		case CGPU_FORMAT_DXBC4_SNORM: return 4;
		case CGPU_FORMAT_DXBC5_UNORM: return 4;
		case CGPU_FORMAT_DXBC5_SNORM: return 4;
		case CGPU_FORMAT_DXBC6H_UFLOAT: return 4;
		case CGPU_FORMAT_DXBC6H_SFLOAT: return 4;
		case CGPU_FORMAT_DXBC7_UNORM: return 4;
		case CGPU_FORMAT_DXBC7_SRGB: return 4;
		case CGPU_FORMAT_PVRTC1_2BPP_UNORM: return 4;
		case CGPU_FORMAT_PVRTC1_4BPP_UNORM: return 4;
		case CGPU_FORMAT_PVRTC2_2BPP_UNORM: return 4;
		case CGPU_FORMAT_PVRTC2_4BPP_UNORM: return 4;
		case CGPU_FORMAT_PVRTC1_2BPP_SRGB: return 4;
		case CGPU_FORMAT_PVRTC1_4BPP_SRGB: return 4;
		case CGPU_FORMAT_PVRTC2_2BPP_SRGB: return 4;
		case CGPU_FORMAT_PVRTC2_4BPP_SRGB: return 4;
		case CGPU_FORMAT_ETC2_R8G8B8_UNORM: return 4;
		case CGPU_FORMAT_ETC2_R8G8B8_SRGB: return 4;
		case CGPU_FORMAT_ETC2_R8G8B8A1_UNORM: return 4;
		case CGPU_FORMAT_ETC2_R8G8B8A1_SRGB: return 4;
		case CGPU_FORMAT_ETC2_R8G8B8A8_UNORM: return 4;
		case CGPU_FORMAT_ETC2_R8G8B8A8_SRGB: return 4;
		case CGPU_FORMAT_ETC2_EAC_R11_UNORM: return 4;
		case CGPU_FORMAT_ETC2_EAC_R11_SNORM: return 4;
		case CGPU_FORMAT_ETC2_EAC_R11G11_UNORM: return 4;
		case CGPU_FORMAT_ETC2_EAC_R11G11_SNORM: return 4;
		case CGPU_FORMAT_ASTC_4x4_UNORM: return 4;
		case CGPU_FORMAT_ASTC_4x4_SRGB: return 4;
		case CGPU_FORMAT_ASTC_5x4_UNORM: return 4;
		case CGPU_FORMAT_ASTC_5x4_SRGB: return 4;
		case CGPU_FORMAT_ASTC_5x5_UNORM: return 5;
		case CGPU_FORMAT_ASTC_5x5_SRGB: return 5;
		case CGPU_FORMAT_ASTC_6x5_UNORM: return 5;
		case CGPU_FORMAT_ASTC_6x5_SRGB: return 5;
		case CGPU_FORMAT_ASTC_6x6_UNORM: return 6;
		case CGPU_FORMAT_ASTC_6x6_SRGB: return 6;
		case CGPU_FORMAT_ASTC_8x5_UNORM: return 5;
		case CGPU_FORMAT_ASTC_8x5_SRGB: return 5;
		case CGPU_FORMAT_ASTC_8x6_UNORM: return 6;
		case CGPU_FORMAT_ASTC_8x6_SRGB: return 6;
		case CGPU_FORMAT_ASTC_8x8_UNORM: return 8;
		case CGPU_FORMAT_ASTC_8x8_SRGB: return 8;
		case CGPU_FORMAT_ASTC_10x5_UNORM: return 5;
		case CGPU_FORMAT_ASTC_10x5_SRGB: return 5;
		case CGPU_FORMAT_ASTC_10x6_UNORM: return 6;
		case CGPU_FORMAT_ASTC_10x6_SRGB: return 6;
		case CGPU_FORMAT_ASTC_10x8_UNORM: return 8;
		case CGPU_FORMAT_ASTC_10x8_SRGB: return 8;
		case CGPU_FORMAT_ASTC_10x10_UNORM: return 10;
		case CGPU_FORMAT_ASTC_10x10_SRGB: return 10;
		case CGPU_FORMAT_ASTC_12x10_UNORM: return 10;
		case CGPU_FORMAT_ASTC_12x10_SRGB: return 10;
		case CGPU_FORMAT_ASTC_12x12_UNORM: return 12;
		case CGPU_FORMAT_ASTC_12x12_SRGB: return 12;
		default: return 1;
	}
}
/* clang-format on */

#ifdef __cplusplus
CGPU_EXTERN_C_END
#endif
